Chapter 5.

Fabrication Process.

5.1.      Introduction

This chapter is devoted to a detailed description of the new fabrication process developed especially as part of this research work, named Multiple Aspect Ratio Structural Integration in Single-Crystal-Silicon, or MASIS. The main motivation to conceive this new process is to fabricate a transmissive MOEMS modulator that enjoys large aperture area and operates at kHz frequencies. Currently, there is no bulk-micromachining process that can support the fabrication of the MOEMS design that has been described in Chapter 4. Figure 5.1 shows the cross section of the process illustrating the implementation of the MOEMS modulator.


Design rules for this process are introduced and thoroughly discussed, as well as the rationale behind each fabrication step in order to make it an effective process for combining multiple aspect-ratio structures within the same device layer. The aspect-ratio is defined as the width of a structure divided by its thickness. The main goal is to fabricate suspended structures that support high-aspect ratio actuators and large area low-aspect ratio shutters, while reducing process complexity by minimizing the number of photolithographic masks. MASIS introduces a simple approach to the fabrication of a variety of micro-systems using Silicon-on-Insulator (SOI) wafers. MASIS is a multi-level bulk-micromachining fabrication process, specially tailored to address the need for transmissive modulators, driven by long-stroke actuators.  The MEMS architecture allows integration of very stiff actuators with very large area shutters. The process addresses the need to reduce the payload mass of the shutters, while maintaining high-aspect ratio of suspension springs and comb fingers of the transducers.  Large aperture shutters are selectively thinned down significantly to achieve the high-frequency low voltage operation.  Furthermore, two process variations derived from SCREAM (Single-Crystal-Reactive-Ion-Etch-and-Metallization) [64] are also discussed, as well as the advantages of different step sequences. MASIS II is introduced as the first alternative that utilizes SOI wafers and requires only a dry-release step. Next, we introduce MASIS III, which requires standard silicon wafers, and also relies on a dry-release step. Both of these processes provide an alternative to MASIS. Lastly, Appendix II includes a number of process details pertaining to fabrication recipes and characterization steps.

 

5.2.    Overview of MASIS

         As an introductory overview to MASIS, the end-result of the process is shown as a series of SEM images, Figures 5.2-5.6. Herein the powerful new concept is introduced in order to illustrate the advantages of combining multiple aspect-ratios of suspended structures in a single device layer.  Moreover, different structural components of the optical modulator on-chip are demonstrated as illustrative examples of the process flow.

Figure 5.2: Shutters, Combs, and Folded Flexures fabricated by the MASIS process.

Figure 5.3: Arrays of suspended shutters over slits fabricated by the MASIS process.

Figure 5.4: Array of comb-drive structure, showing engaged comb-fingers fabricated by the MASIS process.

 

5.3.1.   Fabrication

MASIS introduces a simple approach for the fabrication of the transmissive optical modulators that enjoy a vertical architecture, and can be subsequently integrated as a device layer between an optical source and a photo-detector in order to implement the IHOS. As shown in Figure 5.1, an optical signal travels through the silicon slits, which are alternately shuttered in order to accomplish modulation before photo-detection. The MEMS architecture based on MASIS allows integration of high aspect-ratio actuators with low aspect-ratio shutters. The process is essentially divided into two mask layers. The front mask design, called the Device layer, defines high-aspect ratio structures. In this layer, springs and actuators are defined using the same beam width units, in the 2-4 μm range, while keeping the same thickness of 30 μm. The design rule for the beam width allows all the structures that are below this critical lateral dimension to be suspended above the substrate at a later process release step by a critically timed isotropic etch. In addition, the shutters are defined in this layer, although at a subsequent step the thickness is thinned down to reduce the overall effective mass of the IHOS.  The backside mask design, called the Shutter layer, achieves two functions. The first one is to open the slits through which the optical signal will propagate and will be subsequently shuttered. The second function is to suspend and reduce the mass of the shutters in order to reduce the actuating force as well as to increase the operating frequency. As the mass of the shutters is decreased by an anisotropic silicon etch, the aspect ratio of the shutters, defined by Device layer, is drastically reduced, creating very wide over narrow structures. Hence, as both photolithographic masks are defined two aspect ratio structures are created, as illustrated in Figure 5.6.

 

 

5.3.2.  Fabrication Process Flow

The process starts with standard double-sided polished silicon-on-insulator wafers (SOI) as substrates, which have a device layer of 30 μm, a 2 μm buried oxide layer, and a 300 μm silicon handle. The SOI alternative neither requires passivation, nor sputtering metal, as the device layer is doped heavily. In order to obtain metal contacts, it is possible to deposit metal on a very thin layer all over the device. This step guarantees resistive contacts, avoiding any possible Schottky junctions. All the steps hereinafter mentioned are illustrated in Figure 5.6. For specific details related to the recipes, the reader is also referred to the Appendix II.

• Oxide Mask, step 1 in Figure 5.6. The first step is to grow 2 μm of thermal oxide that act as a mask layer for a subsequent etch of the bulk silicon, for both the device and handle layers of the SOI wafers. Thermal oxide provides a higher quality oxide on each side of the wafer, although it does indeed introduce some residual stress. Depending on the design geometry, in some instances it may be more recommendable to replace the thermal growth by a PECVD oxide. Although this type of oxide is characterized by lower quality, in terms of uniformity and etch selectivity to silicon, it contains less residual stress as the process requires lower temperature.

 

• Backside Photolithography, step 2 in Figure 5.6. The initial photolithographic step involves the backside etch that takes place by spin-coating photo-resist on the backside of the wafer, thereafter developing and exposing the Shutter layer. This mask essentially provides the transmissive architecture for the optical modulation, as it will connect the front and backside of the chip. The goal is to define the transmissive optical windows that will be located underneath the shutters. Once these windows are defined by a backside etch, then the shutters are thinned down 10 mm further by an extended anisotropic etch.

• Pattern Transfer I, steps 2 in Figure 5.6. The first pattern transfer of the design defined from the photo-resist layer to the oxide layer is achieved by anisotropic etch of the oxide utilizing a reactive-ion-etch (RIE), which contains CF4-based plasma. Subsequently, the pattern is defined into silicon by utilizing an inductive-coupled-plasma (ICP) etcher that runs with the Bosch process [85].

 

• Shutter Etch, step 3 in Figure 5.6. The deep silicon etch stops at the buried oxide, which provides a stop-mask in order to compensate for the etch non-uniformities. This is the main reason that SOI wafers have been preferred to standard silicon wafers. The etch variations of the Bosch process lead to 10 percent non-uniformity that is represented as differences in depth of the same design features located in different places on the wafer. A buried oxide layer offers a solution to overcome the Bosch process non-uniformity. The high selectivity of oxide to silicon buffers the variations in etched depths, as all structures attain the same depth after sometime. At this stage some footing effect occurs. The next step is to etch the buried oxide by using a CF4-based RIE, using the same technique described in step 3.

• Shutter Thinning, step 4 in Figure 5.6. Once the buried oxide under the shutters is etched completely, the thinning down process commences. Without an SOI wafer, the etch non-uniformities would not allow to control the shutter thickness accurately. This step is time critical, as the Bosch process will thin down the shutter mass at a rate of about 2 μm per minute. The goal is to thin down to mass leaving only about 10 μm thick shutter.

 

• Front-side Photolithography, step 5 in Figure 5.6. The next step involves the front-side device mask. Up to this stage, the wafer front-side had a 2 μm oxide layer, which also serves as anti-scratching layer. Thereafter, the wafer is subject to its second photolithographic step. This time, however, a thinner photo-resist is utilized since smaller critical dimensions (< 4 μm) are required. 

• Pattern Transfer II, step 6 in Figure 5.6. The next step is to transfer the front-side pattern to the oxide layer. This step is achieved again by the use of a CF4-based RIE that provides the required anisotropic etch.  Subsequently, the silicon is patterned using the Bosch process. The structures are defined down to the buried oxide layer. Again the exposed buried oxide layer is etched using CF4-based RIE. Next, the photoresist layer is removed by using O2-plasma based RIE.  This is required as the wafer will be subject to higher temperatures subsequently.

 

• Silicon Substrate Opening, step 7 in Figure 5.6. The next step involves etching the top and buried silicon dioxide layer. This step leaves a conformal and protective oxide layer on the structures, while silicon windows become exposed in the silicon handle.

• Release, step 7 in Figure 5.6. The release step was achieved by using HF (49 %) for approximately 10 minutes. In order to prevent stiction, the chips were immersed in DI water, and isopropanol. The devices were dried using an oven at 80 C, which was in low vacuum. This was performed in order to avoid the liquid-air interface, and rather obtain a liquid-vacuum interface until all the remaining solutions on the chip surface were evaporated.

 

• Metallization, step 8 in Figure 5.6. This step is required to achieve metal contacts for the  devices, as mentioned earlier. If wire-bonding and an ohmic (non-rectifying) contacts are necessary, then a simple solution to obtain metal pads is based on evaporating a thin layer of metal (<100 nm), such as gold. Such layer guaranties metallic contacts, without compromising the release step or electrical isolation between separate pads.

   

 

5.4.1.   Critical Steps during the Fabrication Process
The MASIS process depends on critical parameters that allow the integration of different aspect-ratio structures in the same device layer. The first critical parameter is related to the photolithographic alignment between the front and backside patterns. This step is crucial in order to match the front design of the actuators with the backside design of the shutter windows.  
Another critical parameter is the verticality of the silicon deep reactive ion etch (DRIE) that defines the shutter windows. The angle of the walls of the backside windows needs to be taken into account to assure a proper structural match between the front and backside patterns.  Moreover, the connection between different aspect-ratio structures is another critical parameter that needs to be considered. The transition between the different aspect-ratio devices is dependent on the Transition Beams, which are also released using the same critically time release step.  
The last critical parameter is related to the release of the actuators in order to obtain high-aspect ratio suspended structures. The release step is based on a critically timed isotropic etch of the buried oxide layer, using HF.
In this section each of these critical parameters is thoroughly discussed in order to demonstrate the successful implementation of the process.

5.4.2.   Alignment
The first critical step of the process is to accurately align the backside design with the front-side design. Alignment marks provide an accurate method to achieve this requirement.  The acceptable estimated error between the front and backside patterns is -/+ 3 mm. We utilized a Karl-Suss MI6 mask aligner to expose the patterns.  Figure 5.8 shows an image of both front and backside alignment marks. The key is to control the placement between front and backside alignment marks. This is one of the reasons that the Shutter Layout mask is firstly defined in the process. As the backside etch is concluded, the front side mask needs to be aligned to the backside design, which is only 10 mm apart from the wafer top. Therefore, higher alignment accuracy can be accomplished by etching the backside first, and then aligning the front-side and the backside designs. Figure 5.9 shows a failed alignment between the front and backside etched patterns.

 

5.4.3.   Verticality of the Backside Etch
The goal of this step is to define the shutter openings by etching silicon windows underneath the shutters. The critical aspect of this step is that the etched windows need to coincide with the corresponding front-side design of the shutters. As the deep silicon etch does not provide a perfectly vertical profile, it is necessary to customize the etch to the required device lateral dimensions.  The windows (optical vias) are etched using the Bosch™ process, which is based on a sequence of combinations of a SF6-based isotropic etch and a subsequent deposition of Teflon-like layer. While several works have dealt with various aspects related to the etch verticality, uniformity, loading-factor effect, and sidewall smoothness [86,87], the issues related to the characterization goes beyond the scope of this work. Herein we only intend to provide a quick summary of the critical parameters of the Bosch process.
Mainly, the verticality can be controlled by variations in the etching and deposition times.  Smoothness can be controlled by the addition of O2 and by reduction of the overall etch and deposition cycles, thereby decreasing the ripple sizes. The average etch-rate is 2 mm per minute, and can be controlled by the power level, while it also contributes to the sidewall smoothness. Finally, the loading-factor effect makes the device layout relate to the etch profile, as differences in trench lateral dimensions lead to variations in the etch verticality and sidewall profile. The interdependence of all these parameters affects the anisotropic properties of the entire etch, and therefore any single variation of a parameter affects the overall profile. Sidewall roughness is not of concern since the wavelength is not a critical parameter for spatial optical modulation.  The only parameter of true concern is the verticality and the etch uniformity across the wafer that mainly depend on the device layout and the times of the etch-deposition cycle. As the Bosch™ process provides undesirable non-uniformity that depends on the layout and wafer location [88,89], it was necessary to run a calibration mask to customize the profile to the device layout.  The calibration design consisted of variations in dimensions of shutter windows for the Shutter layer. The front-side design dimensions required shutter arrays of 50 μm wide separated by 50 μm gaps. The calibration mask varied the shutter widths from a 35 μm to 65 μm in steps of 5 μm, while constantly keeping the same 100 μm pitch.  As the etching for the calibration mask was concluded, an approximate 89 degree-profile verticality was obtained. Figures 5.10-5.12 show the different cross-sections of samples with varying trench widths for a 200 μm deep etch. The actual Shutter layer design needed to accommodate compensated lateral features, which resulted in shutter windows that were 60 μm wide separated by a 40 μm gap. This final design compensation is depicted in

5.4.4.   Transition Beams
The Transition Beams provide the seamless connection between the two distinct aspect ratio structures, and are among the innovative aspects of MASIS. The beam dimensions are 2-4 mm wide and 30 mm long. This critical width is required to release the beams at the same time as the actuators are released. The length of the beam provides the adequate separation between the shutters and the actuators in order to prevent any unwanted etching of actuators.  Therefore, the Transition Beams guarantee that the actuators will have the correct thickness, and prevent any unwanted etching. Figures 5.14-5.16 show the Transition Beams connecting suspended with different aspect-ratios.

5.4.5.  Release Step
The buried oxide layer can be etched using hydro-fluoric acid (HF)-based wet chemistry. The main drawback of this method is that as the gap is very small, capillary forces lead to stiction, which is the main problem for releasing micro-machining structures. Several authors have dealt with various techniques and models to avoid stiction, such as the use of anti-stiction coatings based on self-assembly-monolayers (SAMs) [90,91], vapor HF combined with alcohol [92], HF bath combined with hexane [93,94], and a recent high temperature technique called Flash Release are among the newest methods to release MEMS devices that utilize a buried silicon dioxide sacrificial layer [95]. Nonetheless, there is not a universally recognized standard technique to avoid stiction. We used HF and subsequently replaced it with very low surface tension liquids [96], such as isopropanol, to prevent stiction. As the devices are immersed in solution for about 10 minutes, the HF is replaced with DI water, and subsequently replaced by isopropanol. The next step is to replace the isopropanol with hexane, which offers a lower surface tension.  The final step is to use an oven in vacuum to evaporate the hexane at 85 °C, subsequently the chamber is vented gradually until atmospheric pressure is achieved. This step has proved to be repeatable and reliable.

5.5.       MASIS II
An alternative process to MASIS process using SOI wafers is derived from SCREAM (Single-Crystal-Silicon Reactive Ion Etch and Metallization) [62], which makes use of a passivation technique and a subsequent SF6 based etch to release the silicon devices. Although this proposed process requires a more thorough characterization and it includes more process steps, the main benefit is based on the use of plasma-based chemistry to avoid wet etching. The process runs at low temperature, and also utilizes standard VLSI processes. Figures 5.17-5.18 show all the steps of the process flow. This process can be considered as an alternative for future implementation. The main difference with the standard MASIS process resides in the use of a passivation step and the dry release step. The major distinction factors are summarized as follows:

• Passivation, steps 9 in Figure 5.18. The release step involves passivating the sidewalls of the structuring by means of plasma-enhanced chemical vapor deposition (PECVD) performed at 250 C. This step is required in order to protect the structures from a subsequent isotropic SF6 during the release step. A 1 μm layer of PECVD is deposited on the topside and bottom sides of the structures, while a layer of approximately 150 nm is deposited on the sidewalls. The low temperature process minimizes the residual stress. The devices that are densely positioned are subject to less sidewall deposition than those that are position in open areas. Problems such as unwanted bending may be an issue for fingers structures that are on one side exposed to large openings, and on the other closely position to other structures. Dummy structures may be required in this case to provide a uniform conformal deposition.

 

• Extension Etch and Release, steps 10-11 in Figure 5.18. This useful step is called extension etch, which is required to etch 10 μm down using the Bosch process. The silicon windows become further exposed. The next step is the release step, which is the most critical of all steps. The structures are released by using SF6-based plasma etch. This step is time critical as SF6 etches the structures isotropically. The structures are released, and therefore suspended over the silicon substrate. It is critical to characterize the time of the etch, otherwise an over-etched structure can be obtained. Figure 5.19 shows a SEM image of a comb-drive structure released using SF6. This step is critically timed, implying that an  over-etch may signify a complete structural loss. Figure 5.20 shows an over-etched structure, the silicon has been completely etched, and only the silicon dioxide shell has been preserved.

• Electrical Isolation and Metallization, step 10 in Figure 5.18. This step is required to provide electrical isolation by deposition of a conformal oxide layer using PECVD. A 500 nm layer oxide is deposited horizontally, while a 50 nm oxide layer is deposited on the sidewalls. Finally, the last step involves metallization of the structures by sputtering metal. The metal of choice is aluminum as it does not require any inhesion layer to the oxide. A 200 nm of aluminum is deposited.

 

  

 

 

 

5.6.     MASIS III
Another variation of the standard MASIS is based on the use of standard silicon wafers with a silicon nitride layer as the material for the shutters. Although the process sequence is similar to the one for standard MASIS, it does not require the use of a buried layer as a stop mask. The silicon nitride layer maintains structural support for the shutters, proving the adequate structural rigidity. A clear advantage of this proposed process is that the shutter mass is mainly composed of silicon nitride, thereby increasing the operating modulation frequency. In addition, the process only requires standard wafers, which substantially decrease the fabrication cost, and can be integrated directly on standard VLSI base-line processes. Finally, the opacity of the shutters is achieved by either depositing a thick silicon nitride, greater than 500 nm, or by a subsequent metallization process. In both instances, light can be blocked, achieving a high contrast, maximizing the modulation efficiency. Figure 5.21 provides an overview of the proposed process that also can be considered for future implementation.